A junction gate field-effect transistor (JFET) is a simple type of field effect transistor. JFETs are used advantageously in some low-noise, high input-impedance op-amps and in switching applications. In fact, JFETs offer faster switching speed than bipolar transistors since JFETs are a majority carrier device.
A JFET consists of a long channel of semiconductor material doped so that it contains positive charge carriers (p-type) or negative charge carriers (n-type). In operation, electric current flows from the source to the drain, with the gate determining how much current flows through the device. By applying an increasing negative (for an n-channel JFET) bias voltage to the gate, the current flow from the source to drain can be impeded by pinching off the channel, in effect switching off the transistor.
This behavior is due to the depletion region of the PN junction expanding under the influence of a reverse-bias voltage, eventually occupying the entire width of the channel if the voltage is great enough. This operational behavior is opposite of the bipolar junction transistor or standard CMOS enhancement mode MOSFET transistors, which are normally-off. (JFETs, on the other hand, are normally-on devices where no voltage applied to the gate allows maximum current through the source and drain.)
In order to pinch off the channel, it is necessary to produce a certain voltage in a reverse direction (VGS) of the junction. The precise value of this pinch off voltage varies with individual JFETs, with typical values ranging between 0.5 to 10 V. The appropriate voltage bias can be easily remembered, as the n-channel device requires a negative gate-source voltage (VGS) to switch off the JFET and the p-channel device requires a positive gate-source voltage (VGS) to switch off the JFET.
The larger voltage pn junction avalanche breakdown (10V or greater for gate to drain or gate to source) capabilities make JFETs a candidate for certain applications such as power amplifiers. In comparison, standard CMOS SOI MOSFET devices cannot typically handle 10 V or greater thus making them not ideal candidates for certain applications such as that required for power amplifiers. Also, LD MOS process integration may not be cost effective for power amplifier applications as this process integration adds numerous mask levels and the extended lateral dimension increases circuit area requirement and hence lowers the profit margin.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.